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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDDFR, External Debug Feature Register</h1><p>The EDDFR characteristics are:</p><h2>Purpose</h2>
        <p>Provides top level information about the debug system.</p>

      
        <div class="note"><span class="note-header">Note</span><p>Debuggers must use <a href="ext-eddevarch.html">EDDEVARCH</a> to determine the Debug architecture version.</p></div>
      
        <p>For general information about the interpretation of the ID registers, see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>The power domain of EDDFR is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><h2>Attributes</h2>
        <p>EDDFR is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-63_60">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-59_56">ExtTrcBuff</a></td><td class="lr" colspan="12"><a href="#fieldset_0-55_44">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-43_40">TraceFilt</a></td><td class="lr" colspan="8"><a href="#fieldset_0-39_32">UNKNOWN</a></td></tr><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">CTX_CMPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">SEBEP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">WRPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">PMSS</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">BRPs</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">PMUVer</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">TraceVer</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">UNKNOWN</a></td></tr></tbody></table><h4 id="fieldset_0-63_60">Bits [63:60]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-59_56">ExtTrcBuff, bits [59:56]</h4><div class="field">
      <p>Trace Buffer External Mode Extension. Defined values are:</p>
    <table class="valuetable"><tr><th>ExtTrcBuff</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Trace Buffer Extension not implemented or Trace Buffer External Mode not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Trace Buffer Extension implemented and Trace Buffer External Mode implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If <span class="xref">FEAT_TRBE</span> is not implemented, the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p><span class="xref">FEAT_TRBE_EXT</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>In an implementation that supports AArch64, this field has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.ExtTrcBuff.</p></div><h4 id="fieldset_0-55_44">Bits [55:44]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-43_40">TraceFilt, bits [43:40]</h4><div class="field">
      <p>Armv8.4 Self-hosted Trace Extension version. Defined values are:</p>
    <table class="valuetable"><tr><th>TraceFilt</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Armv8.4 Self-hosted Trace Extension is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Armv8.4 Self-hosted Trace Extension is implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_TRF</span> implements the functionality added by <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.4, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-39_32">Bits [39:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-31_28">CTX_CMPs, bits [31:28]</h4><div class="field">
      <p>Number of breakpoints that are context-aware, minus 1.</p>
    <p>The value of this field is never greater than EDDFR.BRPs.</p>
<p>In an implementation that supports AArch64, this field has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.CTX_CMPs.</p>
<p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more breakpoints that are context-aware are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-27_24">SEBEP, bits [27:24]</h4><div class="field">
      <p>This field either has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.SEBEP or reads as zero.</p>
    </div><h4 id="fieldset_0-23_20">WRPs, bits [23:20]</h4><div class="field">
      <p>Number of watchpoints, minus 1.</p>
    <p>In an implementation that supports AArch64, this field has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.WRPs.</p>
<p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more watchpoints are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p>
<p>The value of <span class="binarynumber">0b0000</span> is reserved.</p>
<div class="note"><span class="note-header">Note</span><p>Only watchpoints 0 to 15 can be accessed in AArch32 state.</p></div></div><h4 id="fieldset_0-19_16">PMSS, bits [19:16]</h4><div class="field">
      <p>This field either has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.PMSS or reads as zero.</p>
    </div><h4 id="fieldset_0-15_12">BRPs, bits [15:12]</h4><div class="field">
      <p>Number of breakpoints, minus 1.</p>
    <p>In an implementation that supports AArch64, this field has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.BRPs.</p>
<p>If <span class="xref">FEAT_Debugv8p9</span> is implemented and 16 or more breakpoints are implemented, this field reads as <span class="binarynumber">0b1111</span>.</p>
<p>The value of <span class="binarynumber">0b0000</span> is reserved.</p>
<div class="note"><span class="note-header">Note</span><p>Only breakpoints 0 to 15 can be accessed in AArch32 state.</p></div></div><h4 id="fieldset_0-11_8">PMUVer, bits [11:8]</h4><div class="field"><p>Performance Monitors Extension version.</p>
<p>This field does not follow the standard ID scheme, but uses the alternative ID scheme described in <span class="xref">'Alternative ID scheme used for the Performance Monitors Extension version'</span></p>
<p>Defined values are:</p><table class="valuetable"><tr><th>PMUVer</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Performance Monitors Extension not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Performance Monitors Extension, PMUv3 implemented.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td><p>PMUv3 for Armv8.1. As <span class="binarynumber">0b0001</span>, and adds support for:</p>
<ul>
<li>Extended 16-bit PMU.PMEVTYPER&lt;n&gt;_EL0.evtCount field.
</li><li>If EL2 is implemented, the <a href="AArch64-mdcr_el2.html">MDCR_EL2</a>.HPMD control.
</li></ul></td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>PMUv3 for Armv8.4. As <span class="binarynumber">0b0100</span>, and adds support for the <a href="AArch64-pmmir_el1.html">PMMIR_EL1</a> register.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td><p>PMUv3 for Armv8.5. As <span class="binarynumber">0b0101</span>, and adds support for:</p>
<ul>
<li>64-bit event counters.
</li><li>If EL2 is implemented, the <a href="AArch64-mdcr_el2.html">MDCR_EL2</a>.HCCD control.
</li><li>If EL3 is implemented, the <a href="AArch64-mdcr_el3.html">MDCR_EL3</a>.SCCD control.
</li></ul></td></tr><tr><td class="bitfield">0b0111</td><td><p>PMUv3 for Armv8.7. As <span class="binarynumber">0b0110</span>, and adds support for:</p>
<ul>
<li>The PMU.PMCR_EL0.FZO and, if EL2 is implemented, <a href="AArch64-mdcr_el2.html">MDCR_EL2</a>.HPMFZO controls.
</li><li>If EL3 is implemented, the <a href="AArch64-mdcr_el3.html">MDCR_EL3</a>.{MPMX,MCCD} controls.
</li></ul></td></tr><tr><td class="bitfield">0b1000</td><td><p>PMUv3 for Armv8.8. As <span class="binarynumber">0b0111</span>, and:</p>
<ul>
<li>Extends the Common event number space to include <span class="hexnumber">0x0040</span> to <span class="hexnumber">0x00BF</span> and <span class="hexnumber">0x4040</span> to <span class="hexnumber">0x40BF</span>.
</li><li>Removes the <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> behaviors if a reserved or unimplemented PMU event number is selected.
</li></ul></td></tr><tr><td class="bitfield">0b1001</td><td><p>PMUv3 for Armv8.9. As <span class="binarynumber">0b1000</span>, and:</p>
<ul>
<li>Updates the definitions of existing PMU events.
</li><li>Adds support for the <a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.UEN control and the PMUACR_EL1 register.
</li><li>Adds support for the <a href="ext-edecr.html">EDECR</a>.PME control.
</li></ul></td></tr><tr><td class="bitfield">0b1111</td><td>
          <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_PMUv3</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_PMUv3p1</span> implements the functionality identified by the value <span class="binarynumber">0b0100</span>.</p>
<p><span class="xref">FEAT_PMUv3p4</span> implements the functionality identified by the value <span class="binarynumber">0b0101</span>.</p>
<p><span class="xref">FEAT_PMUv3p5</span> implements the functionality identified by the value <span class="binarynumber">0b0110</span>.</p>
<p><span class="xref">FEAT_PMUv3p7</span> implements the functionality identified by the value <span class="binarynumber">0b0111</span>.</p>
<p><span class="xref">FEAT_PMUv3p8</span> implements the functionality identified by the value <span class="binarynumber">0b1000</span>.</p>
<p><span class="xref">FEAT_PMUv3p9</span> implements the functionality identified by the value <span class="binarynumber">0b1001</span>.</p>
<p>From Armv8.1, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b0001</span> is not permitted.</p>
<p>From Armv8.4, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b0100</span> is not permitted.</p>
<p>From Armv8.5, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b0101</span> is not permitted.</p>
<p>From Armv8.7, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b0110</span> is not permitted.</p>
<p>From Armv8.8, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b0111</span> is not permitted.</p>
<p>From Armv8.9, if <span class="xref">FEAT_PMUv3</span> is implemented, the value <span class="binarynumber">0b1000</span> is not permitted.</p>
<p>In an implementation that supports AArch64, this field has the same value as <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.PMUVer.</p></div><h4 id="fieldset_0-7_4">TraceVer, bits [7:4]</h4><div class="field">
      <p>Trace support. Indicates whether System register interface to a trace unit is implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>TraceVer</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Trace unit System registers not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Trace unit System registers implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>A value of <span class="binarynumber">0b0000</span> only indicates that no System register interface to a trace unit is implemented. A trace unit might nevertheless be implemented without a System register interface.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>.TraceVer.</p></div><h4 id="fieldset_0-3_0">Bits [3:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h2>Accessing EDDFR</h2><h4>EDDFR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0xD28</span></td><td>EDDFR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered() and !DoubleLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register are <span class="access_level">IMPDEF</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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